1. Field of the Invention
The present invention relates to a method for managing the CMOS (complementary metal oxide semiconductor) clock for a personal computer (PC), and more particularly, to a method for setting the initial time of an operating system (OS) clock operating in a PC.
2. Description of the Related Art
In general, to set the initial time of an OS clock itself, the OS reads the time from a CMOS clock during initial stages of a boot process, and then sets the time read from the CMOS clock as the initial time of the OS clock in the latter stages of a boot process.
Thus, in the earlier method, when the OS is interrupted by another operation after reading the time from the CMOS clock, the time set to be the initial time of the OS clock is a delayed time. In this case, the time managed by the CMOS clock does not match the time managed by the OS clock. Such a discrepancy can cause problems in applications requiring accurate real-time management.
Also, U.S. Pat. No. 3,681,914 to Loewengart, entitled Digital Master Clock, discloses a master clock source which develops clock signals for transmission to a plurality of receiving xe2x80x9cslavexe2x80x9d terminals, wherein the clock signals are periodically scanned and transferred to the slave terminals once each second, thereby to continuously up-date the clock indication at the receiving terminals. U.S. Pat. No. 3,852,953 to Mischiatti, entitled Control And Synchronization Of Clocks, discloses a plurality of slave clocks that are controlled and synchronized from a central station which transmits to each slave clock frequent coded signals each of which conveys in coded form complete information as to the time, and possibly also the date, to be displayed by each slave clock. U.S. Pat. No. 4,322,831 to Peterson, entitled Programmed Digital Secondary Clock, discloses a programmed digital secondary clock which functions as a master clock, a sub-master clock or a slave clock. The master clock is disclosed as maintaining an updated real time count based on a 50 hz or 60 hz AC line or digital oscillator signal, displays the count, and serially transmits digital information representative of the updated real time count for use by a slave clock. It is disclosed that the submaster clock receives an hourly or twice-a-day correction signal from a conventional master clock or a conventional electronic receiver, corrects the real time count, displays the corrected count, and serially transmits digital information representative of the corrected real time count for use by a slave clock. U.S. Pat. No. 5,040,158 to Lee et al., entitled Method For Operating And Maintaining A Clock Of A System, disclose a method of operating and maintaining the clock of the system for determining a reference clock of the system when starting an operation and maintenance processor (OMP), including a first step of requesting and receiving a hardware clock from a network synchronizing processor (NSP), a second step of checking if the received hardware clock does not fall between a predetermined minimum and a predetermined maximum, and if so, providing an alarm message which requires an operator to provide information on a reference clock and if not, requesting reference clocks from all of the processors except an operation and maintenance processor (OMP), and a third step of comparing the hardware clock and the received reference clocks as many times as the number of the received reference clocks, and determining the hardware clock as a reference clock of the system if a difference is less than or equal to a predetermined time for more than the predetermined number of times and if not, providing an alarm message which requires the operator to provide information on a clock as necessary to determine the reference clock of the system. U.S. Pat. No. 5,384,738 to Miyaoka et al., entitled Semiconductor Integrated Circuit Device, disclose a semiconductor integrated circuit device such as a memory device with logic function including a plurality of RAM macrocells and gate arrays, with the RAM macrocells constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. It is disclosed that the semiconductor integrated circuit device includes a clock distribution circuit coupled to receive first clock signals and for outputting second clock signals, with the first clock signals and the second clock signals being of an ECL level. U.S. Pat. No. 5,579,510 to Wang et al., entitled Method And Structure For Use In Static Timing Verification Of Synchronous Circuits, disclose a universal synchronization element used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user""s synchronous digital circuit. It is disclosed that each of these digital circuit elements in a user""s digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element, wherein the propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user""s circuit that the universal synchronization element represents. U.S. Pat. No. 5,805,530 to Youngberg, entitled System, Method, And Device For Automatic Setting Of Clocks, discloses a system, method and device for providing automatic setting of time of day and other information used by clocks and clock circuits/functions found in host devices such as household appliances, automobiles, wrist watches, computers and other electronic devices. The system is disclosed as including a remote host time piece device for maintaining the time of day and has a timebase with a reference from an electronic input, and includes a master time piece for obtaining the correct time and for transmitting the correct time to the remote host timepiece device. It is disclosed that circuitry is included in the system for accepting the transmission of the correct time from the master time piece and for setting the time of day in the remote host time piece device to the correct time transmitted from the master time piece. Also, included in the system is circuitry, remote from the master time piece, for initiating from the master time piece the transmission of the correct time to the remote host time piece device upon the occurrence of at an event, such that the master time piece transmits to the remote host time piece device an accuracy number that is used to determine based upon a selected tolerance whether the transmitted correct time from the master time piece is to be accepted for setting the time of day in the remote host time piece device to the correct time transmitted from the master time piece.
To solve the above problem, it is an objective of the present invention to provide a method for setting the initial time of an OS clock so that the time managed by the CMOS clock in a PC matches the time managed by the OS clock.
Accordingly, to achieve the above objective and other objectives, there is provided a method for setting the initial time in a clock managed by an operating system in a personal computer system, which have the steps of: turning on the power and checking the ROM-BIOS (read only memory-basic input/output system) of the personal computer system; booting the operating system; reading the current time from a CMOS clock of the personal computer system; setting the time read from the CMOS clock as the initial time in a clock managed by the operating system; and again reading the current time from the CMOS clock and comparing the read current time with the time of the clock managed by the operating system and, if the times do not match each other, repeating the steps of reading the current time from the CMOS clock and setting the time read from the CMOS clock in the clock managed by the operating system.